In the semiconductor industry, fabrication of a semiconductor device generally includes processing a semiconductor wafer, which includes front-end-of-line (FEOL) and back-end-of-line (BEOL) processing during which electronic components (e.g., transistors, resistors, capacitors) are patterned in the wafer and interconnected to form integrated circuits—ICs). After processing the wafer, the wafer is broken into individual die that are then packaged.
As part of the BEOL processing, a wafer may undergo damascene processing to form electric interconnects such as conductive lines, contacts or vias. To form a conventional damascene structure, a dielectric layer is formed over a substrate having a conductive region thereon. An opening is formed in the dielectric layer. The opening can be a contact opening, a via opening, a conductive line trench or a damascene opening. The opening exposes a portion of the conductive region in the substrate. A metallic layer is formed over the substrate and completely fills the opening. In one example, this layer may be formed by first forming a thin metallic seed layer followed by a thicker metallic layer that at times may be referred to as a “damascene layer.” In one example, the thin seed layer of copper may be formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD), and the damascene layer of copper may be formed by electro-chemical deposition (ECD) (electroplating).
After applying metallic layer over the substrate, the wafer may be cleaned by rinsing off the wafer to remove residues generated during application of the metallic layer. The cleaned wafer may be dried such as by spinning the wafer. And finally, the wafer is annealed and chemical-mechanical polishing (CMP) is conducted to remove excess metallic material outside the opening.
One common wafer generally includes major front and back surfaces joined by a circumferential side that is often beveled. During damascene processing, it is often desirable to form the metallic filling layer such that its electrodeposited layer is close to but not on the side of the wafer. Likewise, then, it is generally undesirable for the electrodeposited layer to extend onto the side of the wafer. Techniques have been developed for removing any portion of the electrodeposited layer formed on the side of the wafer, but it is generally desirable to improve upon existing techniques.